ISACSimulator Full-Scale 6G Digital Twin & Hardware-in-the-Loop Emulation

ISACSimulator powers large-scale hardware-in-the-loop (HIL) emulation and real-time digital twins for 6G ISAC, connecting physical software-defined radios and multi-node testbeds to live synthetic environments.

ISACSimulator Full-Scale HIL Testbed Architecture

ISAC Core: HIL Emulation Core — Real-Time FPGA Channel & Echo Generator

6G ISAC Nodes & Beamforming Subsystems

Multi-Chassis USRP / SDR Pool
Real-Time FPGA Channel Emulator
Dynamic Radar Target Synthesizer
Digital Twin Scenario Orchestrator
Automated Conformance Test Harness

Architectural Layers & Waveform Pipelines

Layer 1: Dual-Functional Waveform & Baseband (OTFS / OFDM-Radar / Fractional Fourier Transform / Ambiguity Function): Orthogonal Time Frequency Space (OTFS) modulation and fractional chirp synthesis achieving zero inter-carrier interference under severe Doppler spreads.
Layer 2: Massive MIMO & Beamforming Frontends (140 GHz D-Band / True-Time-Delay (TTD) / Hybrid Analog-Digital Beamforming): Sub-THz active phased array architectures with true-time-delay beam-squint mitigation, simultaneous communication data beams and pencil radar tracking lobes.
Layer 3: Radar Signal Processing & 4D Point Cloud (2D-FFT Range-Doppler / MUSIC AoA / CFAR Detection / Micro-Doppler Extraction): Sub-decimeter range and velocity resolution, constant false-alarm rate (CFAR) detection, and micro-Doppler biomechanical gait and drone propeller classification.
Layer 4: Network Sensing Orchestration & 3GPP Rel-19 (3GPP Rel-19 ISAC Core / Sensing Function (SF) / Reconfigurable Intelligent Surfaces (RIS)): Cell-free collaborative radar networks, dynamic time-frequency resource allocation balancing communication SLA against radar revisit time.

Sensing Telemetry & Benchmarks: <5 cm (Range Resolution) | 0.1 m/s (Velocity Precision) | <10 ms (Radar Frame Latency) | 3GPP Rel-19 (Global Standard)

Full-Scale 6G Digital Twin & Hardware-in-the-Loop in ISACSimulator

Validating multi-carrier ISAC systems requires transitioning from offline algorithmic code to hard real-time physical emulation. ISACSimulator combines high-bandwidth FPGA channel emulators, physical software-defined radio (SDR) chassis, and distributed microservice digital twins to subject production basebands to hundreds of simultaneous dynamic radar targets, multi-path fading, and intense V2X network traffic.

Core Engineering Areas

Multi-Chassis SDR Hardware-in-the-Loop (HIL) Emulation — Connecting physical commercial baseband ASICs and SDR transceivers to wideband FPGA channel emulators operating with sub-nanosecond phase synchronization.
Dynamic 3D Scenario Generation and Sensor Fusion Emulation — Orchestrating complex real-world test cases including multi-vehicle highway pileups, drone swarm navigation, and storm-degraded cellular handoffs.
Automated Conformance Testing and 3GPP Standards Verification — Automated execution of standard conformance test suites measuring sensing resolution, false alarm rates, EVM, and block error rates (BLER).